A 320 Gbps board level Data Sourcing System FPGA Design
Lucas Arruda Ramalho1; Aílton Akira Shinoda1; Vitor Finotti Ferreira2; André Muller Cascadan2
1 São Paulo State University, UNESP, Ilha Solteira, SP; 2 São Paulo State University, UNESP, Barra Funda, SP
Resumo
The evolution of FPGA Multi Gigabit Transceivers (MGT) brought opportunities for data formatter and data acquisition projects in several areas. The newer FPGA families are capable to handle Gigabit I/Os implemented over high speed serial link protocols and becoming the future downstream processors. The digital systems created for that purpose need to be reliable and synchronous between dozens of channels and boards. In order to have instruments to test these projects, this work implemented an emulator that is capable to produce data synchronized in 40 channels up to 8 Gbps each. This system was built using the Pulsar 2b, a custom ATCA FPGA-based board designed by Fermilab, to be a scalable high speed link processor system. The results showed that the system is able to provide data, and to measure synchronization, latency and bit error rate of the MGTs.
Palavras-chave: Emulator System; ATCA; FPGA; High Speed Serial Link Protocol